This invention relates to integrated circuit devices and fabrication methods, and more particularly to integrated circuit devices and fabrication methods that use plasma processing.
Plasma processing is widely used in fabricating integrated circuit devices. Plasma processing may include dry etching, thin film deposition, ashing and blanket etching. In particular, dry etching is widely used in fabricating highly integrated devices because anisotropic etching may be produced, to thereby allow submicron devices to be formed.
Unfortunately, plasma processing may also produce undesirable damage in the integrated circuit device. More particularly, since the plasma comprises a mix of charged particles, the particles may undesirably accumulate on certain surfaces. Thus, a conductive line such as a gate electrode of an integrated circuit field effect transistor may accumulate undesired charges thereon during plasma processing. The plasma charges may flow toward the edge of the conductive line in an effect known as the xe2x80x9cantenna effectxe2x80x9d, and thereby damage an underlying insulator. Integrated circuit field effect transistors may be particularly susceptible to this damage because the insulated gate electrode thereof generally includes a very thin gate insulating layer between the gate electrode and the surface of the integrated circuit. This gate insulator damage may degrade the properties of the field effect transistor and/or reduce the yield of the integrated circuit manufacturing process. Moreover, the degraded performance may not become apparent until after the integrated circuit is placed in the field, thereby degrading the reliability to the end user.
In order to reduce plasma processing damage, it is known to connect a junction diode to a conductive line such as a gate electrode on an integrated circuit substrate. Thus, for an NMOS transistor, it is known to add an NP diode and for a PMOS transistor it is known to add a PN diode, to thereby allow the charges generated on the conductive line during the plasma process to dissipate into the integrated circuit substrate through the junction diode. The addition of a junction diode to reduce plasma processing damage is illustrated in FIGS. 1-4.
FIGS. 1-3 are top and cross-sectional views of a conventional integrated circuit device that includes a diode to reduce plasma processing damage. FIG. 2 is a cross-sectional view of FIG. 1 taken along the line 2-2xe2x80x2 and FIG. 3 is a cross-sectional view of FIG. 1 taken along the line 3-3xe2x80x2.
Referring to FIGS. 1-3, a conventional integrated circuit field effect transistor, such as an NMOS transistor, includes a well 12 of first conductivity type, here p-type, in an integrated circuit substrate such as a silicon semiconductor substrate 10. A field oxide layer 14 is formed in the integrated circuit substrate. A gate insulating layer 16 is formed on the face of the integrated circuit substrate. A gate electrode such as an L-shaped gate electrode 18 is formed. The gate electrode 18 may include sidewall spacers 20. Spaced apart source and drain regions 22 of second conductivity type, here n-type, are formed on opposite sides of the gate electrode 18. A second conductivity type bulk region 24 may be included in the first conductivity type well 12. A junction diode is formed by forming a second conductivity type region 26, here n-type, in the first conductivity type well 12.
Continuing with the description of FIGS. 1-3, an interlayer insulating layer 28 is formed on the integrated circuit substrate, including on the gate electrode 18. The interlayer insulating layer 28 includes contact holes therein that individually expose the bulk region 24, the source/drain regions 22, the second conductivity type region 26 of the junction diode, and the gate electrode 18 on the field oxide layer 14. Conductive plugs such as tungsten plugs 30 are formed in the contact holes. A first metallization line 32a is formed on the interlayer insulating layer 28 opposite the integrated circuit substrate 10 and is connected to the gate electrode 18 and the second conductivity type region 26 of the junction diode. A plurality of second metallization lines 32b are formed to individually connect the bulk region 24, the source/drain regions 22 and the second conductivity type region 26 of the junction diode via the conductive plugs 30. A second insulating layer 34 is then formed on the interlayer insulating layer 28 including on the first and second metallization lines 32a and 32b. 
FIG. 4 is an equivalent circuit of the integrated circuit device of FIGS. 1-3. As shown in FIG. 4, the gate electrode G of the NMOS transistor is electrically connected to the NP junction diode by the first metallization line 32a (FIGS. 1 and 3). Plasma charges that are generated during plasma processing therefore flow into the substrate through the diode. Thus, when plasma processing is performed in order to form the gate electrode, plasma charges can flow into the substrate through the junction diode, thereby reducing damage from the plasma.
Unfortunately, the use of a junction diode that is connected to a conductive line such as a gate electrode may not prevent all plasma processing-induced damage to the underlying insulator. As the integration density of integrated circuit devices continues to increase, and the thickness of the gate insulator continues to decrease, this remaining plasma processing damage may continue to impact the performance, yield and/or reliability of the integrated circuit devices.
It is therefore an object of the present invention to provide improved integrated circuit devices and fabrication methods therefor.
It is another object of the present invention to provide integrated circuits and fabrication methods that can reduce damage during plasma processing.
It is another object of the present invention to provide integrated circuit devices and fabrication methods that can reduce damage during plasma processing compared to devices that include a diode connected to a conductive line.
These and other objects are provided according to the present invention by an integrated circuit that includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes means for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing.
It has been found, according to the present invention, that although the use of a single diode may allow one of the positive and negative charges to dissipate into the substrate, the other of the positive and negative charges does not dissipate into the substrate, because the diode prevents flow of the other of the positive and negative charges. For example, for an NP diode, negative charges can flow freely toward the substrate from the conductive line, but positive charges do not flow. Thus, the positive charges can damage the underlying insulating layer. The same phenomenon may take place when a PN diode is connected to the gate electrode of a PMOS transistor, except that positive charges flow into the substrate but negative charges are trapped.
In sharp contrast, the present invention allows both positive and negative charges to flow from the conductive line into the substrate during plasma processing. After plasma processing, one of the first and second diodes is disconnected so that only one type of charge, such as negative charge, is conducted on the conductive line during normal operation of the integrated circuit. Thus, normal operation of the integrated circuit need not be degraded.
Accordingly, integrated circuits are fabricated according to the present invention by forming a conductive line on an integrated circuit substrate and first and second diodes in the integrated circuit substrate that are electrically connected to the conductive line in antiparallel. Then, plasma processing is performed on the integrated circuit substrate including the conductive line and the first and second diodes, such that the first and second diodes dissipate both positive and negative charges on the conductive line during the plasma processing. Then, one of the first and second diodes is disconnected from the conductive line after performing the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after performing the plasma processing.
Many conventional techniques may be used to disconnect the one of the first and second diodes from the conductive line after plasma processing. However, preferably, a fuse is provided that electrically connects the one of the first and second diodes to the conductive line. The fuse may be provided by reducing the width of the conductor that electrically connects the one of the first and second diodes to the conductive line. The fuse may be activated by current/voltage, by laser or by other conventional means.
More specifically, integrated circuits according to the present invention include an integrated circuit substrate having a first well of first conductivity type and a second well of second conductivity type at a face thereof. Spaced apart source and drain regions are included in the first well, at the face. An insulated gate electrode is included on the face between the spaced apart source and drain regions. A first region of second conductivity type is included in the first well. The first region and the first well form a first junction diode. A second region of first conductivity type is included in the second well. The second region and the second well form a second junction diode. A conductive structure extends between the insulated gate electrode, the first region and the second region, to thereby electrically connect the insulated gate electrode, the first region and the second region to one another. The conductive structure between the first and second regions includes a narrow portion relative to the conductive structure between the first region and the insulated gate electrode. An insulating layer also may be provided on the conductive structure, opposite the integrated circuit substrate. The insulating layer may include a hole that exposes the narrow portion. The first and second wells preferably are adjacent one another to define a boundary therebetween, and the narrow portion preferably extends across the boundary.
In more detail, the conductive structure preferably comprises an interlayer insulating layer on the first and second wells and on the insulated gate electrode, and first, second and third conductive plugs that extend through the interlayer insulating layer, to electrically contact the insulated gate electrode, the first region and the second region, respectively. A metallization line is provided on the interlayer insulating layer that electrically connects the first, second and third conductive plugs. The metallization line between second and third conductive plugs includes a narrow portion relative to the metallization line between the first and second plugs. A second insulating layer may be provided on the metallization line opposite the interlayer insulating layer. The second insulating layer may include a hole therein that exposes the narrow portion.
Thus, plasma processing is performed on the integrated circuit substrate including the conductive structure and the first and second diodes, such that the first and second diodes dissipate both positive and negative charge on the conductive line during the plasma processing. The narrow portion is then opened after performing the plasma processing, to thereby disconnect the second junction diode from the insulated gate electrode after performing the plasma processing. Improved integrated circuit devices and fabrication methods may thereby be provided that can reduce and preferably eliminate damage that is caused by positive and negative charged particles that accumulate on conductive lines during plasma processing.